Doi.org/10.1016/j.micpro.2017.03.003
Target ArticleEdit
Power modeling for high performance network-on-chip architectures ; Yaseer Arafat Durrani Teresa Tiesgo; NULL; 03/08/2017; https://doi.org/10.1016/j.micpro.2017.03.003
ReasonsEdit
Note: Reasons not yet here included, but you are welcome to insert this information whenever you wish.